Tag Archive
Agilent Sells Network Solutions Test Business to JDSU ~ EDA Geek
JDSU announced that it has entered into a definitive agreement to acquire the Network Solutions communications test business of Agilent,… »
Mid-Range, 3G Wireless Apple iPad Costs Only $287 to Manufacture …
The mid-range, 3G-wireless version of Apple Inc.’s upcoming iPad is expected to carry a combined Bill of Materials (BOM) and… »
ASIA Company Deploys Mentor Graphics CHS Tools for Wire Harness …
Mentor Graphics Corporation (NASDAQ: MENT) announced that ASIA Company, a Korea-based wire harness supplier, has made dramatic gains by deploying… »
austriamicrosystems Broadens Deployment of Cadence EDA Tools ~ EDA …
Cadence Design Systems Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that austriamicrosystems (SIX: AMS), a leading… »
Aeroflex Deploys Synopsys CustomSim Unified Circuit Simulation …
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Aeroflex… »
Cadence Leverages STARC Regression Suites for Chip Design ~ EDA Geek
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and Semiconductor Technology and Academic Research Center… »
Synopsys to Present and Showcase at DesignCon 2010 ~ EDA Geek
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, will be demonstrating… »
Renesas Selects Cadence Virtuoso for Mixed-Signal, Analog Design …
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Renesas Technology Corp. has upgraded… »
Hella Aglaia Selects Impulse C to FPGA Xilinx FPGAs for 3D …
Impulse Accelerated Technologies announced that Hella Aglaia has completed a design for a Hella Aglaia computer vision 3D automatic passenger… »
Solido Design Automation Opens Up Variation Designer Platform …
Solido Design Automation, a leading developer of software for reducing variation risk in nanometer designs at the transistor level, has… »